《電子技術(shù)應(yīng)用》
您所在的位置:首頁(yè) > 嵌入式技術(shù) > 解決方案 > ADI ADSP-BF592 Blackfin處理器開(kāi)發(fā)評(píng)估方案

ADI ADSP-BF592 Blackfin處理器開(kāi)發(fā)評(píng)估方案

2012-02-02
關(guān)鍵詞: DSP Blackfin BF592

ADI公司的ADSP-BF592是低成本Blackfin處理器,具有適用于工業(yè)和通用應(yīng)用的最佳的外設(shè)指令,具有高性能的高達(dá)400MHz Blackfin處理器,兩個(gè)16位MAC,兩個(gè)40位ALU,四個(gè)8位視頻ALU和40位移位器.主要應(yīng)用在消費(fèi)類音頻設(shè)備,低成本圖像設(shè)備,智能電表,消費(fèi)類手持設(shè)備,醫(yī)療設(shè)備和汽車駕馭輔助系統(tǒng).本文介紹了ADSP-BF592主要特性,方框圖和Blackfin處理器內(nèi)核框圖以及ADSP-BF592 Blackfin處理器評(píng)估板框圖,電路圖和材料清單(BOM).

ADSP-BF592: Low Cost Blackfin with Optimized Peripheral Set for Industrial and General Purpose Applications

The ADSP-BF592 processor is a member of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual- MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.

The ADSP-BF592 processor is completely code compatible with other Blackfin processors. The ADSP-BF592 processor offers performance up to 400 MHz and reduced static power consumption.

The ADSP-BF592 processor is a highly integrated system-on-a chip solution for the next generation of digital communication and consumer multimedia applications. By combining industry standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. The system peripherals include a watchdog timer; three 32-bit timers/counters with PWM support; two dual-channel, full-duplex synchronous serial ports (SPORTs); two serial peripheral interface (SPI) compatible ports; one UART® with IrDA support; a parallel peripheral interface (PPI); and a 2-wire interface (TWI) controller.

Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which provides the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.

ADSP-BF592主要特性:

Up to 400MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter

RISC-like register and instruction model for ease of programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O operations

Off-chip voltage regulator interface

64-lead (9 mm × 9 mm) LFCSP package

MEMORY

68K bytes of core-accessible memory

64K byte L1 instruction ROM

Flexible booting options from internal L1 ROM and SPI memory or from host devices including SPI, PPI, and UART

Memory management unit providing memory protection

PERIPHERALS

Four 32-bit timers/counters, three with PWM support

2 dual-channel, full-duplex synchronous serial ports (SPORT), supporting eight stereo I2S channels

2 serial peripheral interface (SPI) compatible ports

1 UART with IrDA support

Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats

2-wire interface (TWI) controller

9 peripheral DMAs

2 memory-to-memory DMA channels

Event handler with 28 interrupt inputs

32 general-purpose I/Os (GPIOs), with programmable hysteresis

Debug/JTAG interface

On-chip PLL capable of frequency multiplication

ADSP-BF592應(yīng)用領(lǐng)域:

Consumer Audio

Low-cost imaging devices

Smart Meters

Consumer Handheld Devices

Medical Equipment

Automotive Driver Assistance Systems

圖1. ADSP-BF592處理器框圖

圖2. ADSP-BF592 Blackfin處理器內(nèi)核框圖

ADSP-BF592 Blackfin處理器評(píng)估板

Blackfin processors embody a new type of embedded processor designed specifically to meet the computational demands and power constraints of today’s embedded audio, video, and communications applications. They deliver breakthrough signal-processing performance and power efficiency within a reduced instruction set computing (RISC) programming model.

Blackfin processors support a media instruction set computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics. Blackfin processors deliver signal-processing performance in a microprocessor-like environment.

Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit RISC instruction set, dual 16-bit multiply accumulate (MAC) DSP functionality, and eight-bit video processing performance that had previously been the exclusive domain of very-long instruction word (VLIW) media processors.

The evaluation board is designed to be used in conjunction with the VisualDSP++ ® development environment to test capabilities of the ADSP-BF592 Blackfin processors. The VisualDSP++ development environment aids advanced application code development and debug, such as:

• Create, compile, assemble, and link application programs written in C++, C, and ADSP-BF592 assembly

• Load, run, step, halt, and set breakpoints in application programs

• Read and write data and program memory

• Read and write core and peripheral registers

• Plot memory

Access to the processor from a personal computer (PC) is achieved through a USB port or an external JTAG emulator. The USB interface provides unrestricted access to the ADSP-BF592 processor and evaluation board peripherals. Analog Devices JTAG emulators offer faster communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products.

The ADSP-BF592 EZ-KIT Lite provides example programs to demonstrate the evaluation board capabilities.

The ADSP-BF592 EZ-KIT Lite installation is part of the VisualDSP++ 5.0. An EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days.


圖3.評(píng)估板EZ-KIT Lite外形圖

ADSP-BF592 Blackfin處理器評(píng)估板特性:

• Analog Devices ADSP-BF592 Blackfin processor

• Core performance up to 400 MHz

• 64-lead LFCSP

• Programmable VDDINT core power

• Analog Devices AD5258 TWI digital potentiometer

• Analog Devices ADP1715 low dropout linear regulator

• SPI external flash memory

• Numonyx M25P16 – 16 Mb

• Audio codec

• Analog Devices SSM2603 stereo, 24-bit analog-to-digital and digital-to-analog converters

• Highly efficient headphone amplifier

• Stereo line input and monaural microphone input

• Universal asynchronous receiver/transmitter (UART)

• ADM3202 RS-232 line driver/receiver

• DB9 female connector

• LEDs

• Eight LEDs: one board reset (red), three general-purpose (amber), one power (green), one battery good indicator (green), one battery low indicator (amber) and one battery charging indicator (amber)

• Push buttons

• Four push buttons: one reset, two programmable flags, and one wake-up with debounce logic

• Expansion interface II

• Next generation of the expansion interface design, provides access to most of the processor signals

• Land grid array

• Easy probing of all port pins

• Other features

• JTAG ICE 14-pin header

• Battery charger for a 3.7V single sell Li-Ion battery

The EZ-KIT Lite is designed to demonstrate the ADSP-BF592 Blackfin processor capabilities. The processor has an I/O voltage of 3.3V. The core voltage of the processor is controlled by an Analog Devices ADP1715 low dropout regulator (LDO) and an Analog Devices AD5258 digipot, which is configurable over the 2-wire interface (TWI) signals. Refer to thepower-on-self test (POST) example in the ADSP-BF592 installation directory of VisualDSP++ for information on how to set up the TWI interface.

The core voltage and clock rate can be set up on the fly by the processor. The input clock is 25 MHz. The core and system clock are programmable via the PLL_DIV register of the processor. The core clock runs at a maximum of 400 MHz.

圖4.評(píng)估板EZ-KIT Lite方框圖

圖5.評(píng)估板EZ-KIT Lite電路圖(1)

圖6.評(píng)估板EZ-KIT Lite電路圖(2)

圖7.評(píng)估板EZ-KIT Lite電路圖(3)

圖8.評(píng)估板EZ-KIT Lite電路圖(4)

圖9.評(píng)估板EZ-KIT Lite電路圖(5)

圖10.評(píng)估板EZ-KIT Lite電路圖 (6)

評(píng)估板EZ-KIT Lite材料清單(BOM):








詳情請(qǐng)見(jiàn):
http://www.analog.com/static/imported-files/data_sheets/ADSP-BF592.pdf

http://www.analog.com/static/imported-files/eval_kit_manuals/ADSP-BF592_EZ-KIT_%20Lite_%20Rev1.0.pdf
 



本站內(nèi)容除特別聲明的原創(chuàng)文章之外,轉(zhuǎn)載內(nèi)容只為傳遞更多信息,并不代表本網(wǎng)站贊同其觀點(diǎn)。轉(zhuǎn)載的所有的文章、圖片、音/視頻文件等資料的版權(quán)歸版權(quán)所有權(quán)人所有。本站采用的非本站原創(chuàng)文章及圖片等內(nèi)容無(wú)法一一聯(lián)系確認(rèn)版權(quán)者。如涉及作品內(nèi)容、版權(quán)和其它問(wèn)題,請(qǐng)及時(shí)通過(guò)電子郵件或電話通知我們,以便迅速采取適當(dāng)措施,避免給雙方造成不必要的經(jīng)濟(jì)損失。聯(lián)系電話:010-82306118;郵箱:aet@chinaaet.com。
主站蜘蛛池模板: 操美女视频免费网站| 波多野结衣aa| 国产欧美日韩成人| bollywoodtubesexvideos| 日本在线理论片| 亚洲欧美一区二区三区在线| 精品香蕉一区二区三区| 国产成人精品福利网站在线 | 国产精品一区二区久久沈樵| www久久com| 日本三级欧美三级| 亚洲午夜精品久久久久久浪潮 | 在线私拍国产福利精品| 中文在线免费观看| 日韩在线观看完整版电影| 亚洲欧美另类综合| 男生的肌肌桶女生的肌肌| 国产一国产二国产三国产四国产五| 97午夜理伦片在线影院| 思思99热在线观看精品| 久久国产成人精品国产成人亚洲 | 欧美日韩人妻精品一区二区三区| 出差被绝伦上司侵犯中文字幕| 青青草成人免费| 国产片欧美片亚洲片久久综合| 99久久99久久精品国产片果冻| 已婚同事11p| 久久久久亚洲av无码专区| 最新电影天堂快影eeuss| 亚洲欧美中文日韩综合| 白医生的控制欲| 啊灬啊别停灬用力啊动视频| 高中生被老师第一次处破女| 国产精品一区二区久久| 99re热在线观看| 女人张开腿给男人桶爽免费| 中文字幕你懂的| 日本特黄特色特爽大片老鸭| 亚洲av乱码一区二区三区| 欧美日韩a级片| 亚洲精品中文字幕无码AV|