中圖分類號：TN401
文獻(xiàn)標(biāo)志碼：A
DOI: 10.16157/j.issn.0258-7998.223103
中文引用格式： 趙嘉禾，宋潤泉，許惟超，等. 基于OCP的輕量級多主從跨時鐘域片上總線設(shè)計[J]. 電子技術(shù)應(yīng)用，2023，49(2)：45-49.
英文引用格式： Zhao Jiahe，Song Runquan，Xu Weichao，et al. A clock domain crossing multi-master-slave lightweight on-chip bus based on OCP[J]. Application of Electronic Technique，2023，49(2)：45-49.

A clock domain crossing multi-master-slave lightweight on-chip bus based on OCP

Abstract： The open core protocol (OCP) bus can be applied to decouple IP core functions and the interfaces to realize the plug-and-play function. Aiming at the synchronization problem when the OCP is connected to asynchronous clock domain, a lightweight synchronization interface is developed, which not only synchronizes the control signals but also reduces the hardware consumption caused by data buffer across the clock domain. In view of the scalability of the point-to-point OCP bus, the enhanced clock-domain-crossing OCP bus is deployed on the AMBA High-performance Bus (AHB)，which is interconnected by the shared bus, in order to realize multi-master-slave multi-clock transmission. It is proved by simulation that the enhanced clock-domain-crossing OCP-AHB bus can transmit data correctly, which is able to be rapidly deployed in the next step.

Key words : system on chip；clock domain cross；multiple master slave；open core protocol