中圖分類號：TP393 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.233808 中文引用格式： 劉佳寧，單偉，劉金鵬. PCIe總線DMA高速傳輸系統(tǒng)的設計與實現(xiàn)[J]. 電子技術應用，2023，49(12)：85-89. 英文引用格式： Liu Jianing，Shan Wei，Liu Jinpeng. Design and implementation of DMA high-speed transmission system based on PCIe[J]. Application of Electronic Technique，2023，49(12)：85-89.
Design and implementation of DMA high-speed transmission system based on PCIe
Liu Jianing，Shan Wei，Liu Jinpeng
China Electronics Technology Group Corporation 58th Research Institute， Wuxi 214035， China
Abstract： According to the issue of limited and low-effective peripheral bandwidth in transmission system, this paper designs a DMA high-speed transmission system based on PCIe. Taking FPGA as control unit, the transaction layer protocol of full duplex DMA read and write channels is realized with the time-sharing control method which combined PIO and DMA. Then PIO receives the instructions and translates real-time status information, DMA controller takes charge of the transfer size with a two-section-slice clipping mechanism, transmit engine arbitrates all of the requests according to the priority logic, receive engine performs real-time management of completion packet by caching the TAG label, and solves out-of-order problem. At last, the transmission speed is tasted by means of clock counter， and the restriction factors affecting read/write transmission speed are analyzed. By the practical verification, the effective bandwidth of DMA write has reached 75%, which is very close to the theoretical limit of 80%, and DMA read effective bandwidth has also reached 60%. The design solved the problem of bandwidth limitation in high-speed transmission system, and affords certain engineering application value.
Key words : PCIe bus；DMA；two-section slice；request arbitration；out-of-order
