中圖分類號：TN919.3 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234079
中文引用格式： 文豐，李晴爽，李輝景. 基于UltraScale架構(gòu)FPGA的DDR3用戶接口優(yōu)化系統(tǒng)[J]. 電子技術(shù)應(yīng)用，2023，49(12)：98-102.
英文引用格式： Wen Feng，Li Qingshuang，Li Huijing. DDR3 user interface solution based on UltraScale architecture FPGA[J]. Application of Electronic Technique，2023，49(12)：98-102.

DDR3 user interface solution based on UltraScale architecture FPGA

Abstract： In order to meet the needs of real-time and high-speed data acquisition cache in the field of high-speed transmission system combined with Xilinx′s XCKU060 based on Ultrascale architecture, on the basis of understanding the definitions and characteristics of the node corresponding to FPGA and DDR3, this design allocates all the pins that connect them properly, and make them run successfully on IP cores. For the convenience of users in the use of software, based on the above, read-write FIFO and read-write logic control modules are introduced to the controller interface, optimizing its interface encap sulation.The read-write process is tested in VIVADO software. The method can meet the high speed, large capacity, real-time data read-write requirements, and take advantage of the flexibility of DDR3 storage.

Key words : XCKU060；DDR3 SDRAM；read-write scheme optimization；IP core application；FPGA pin assignment；data acquisition and storage