中圖分類號(hào)：TN492；TN722.7.5 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.256340
中文引用格式： 劉曉禹，韓程浩，阮文武，等. 19~21 GHz GaAs高線性功率放大器MMIC[J]. 電子技術(shù)應(yīng)用，2025，51(4)：72-78.
英文引用格式： Liu Xiaoyu，Han Chenghao，Ruan Wenwu，et al. 19~21 GHz GaAs high linearity power amplifier MMIC[J]. Application of Electronic Technique，2025，51(4)：72-78.

19~21 GHz GaAs high linearity power amplifier MMIC

Abstract： Based on a technology of 0.15 μm GaAs high electron mobility transistor (pHEMT), a 19~21 GHz high linearity power amplifier MMIC was demonstrated in this paper. In the scenario of signal transmission with high peak-to average power ratio（PAPR）,the efficiency and linearity of power amplifier（PA）have a critical impact on RF front-end performance. The amplifier incorporates a cold-mode linearization circuit cascaded at the power amplifier gate to compensate for the amplifier's phase distortion characteristics, thereby enhancing linearity and efficiency. To address the voltage sensitivity issue of the cold mode, an on-chip active voltage stabilization and temperature compensation bias circuit is employed to expand the dynamic range, reduce large dynamic distortion, and mitigate the deterioration of linearity caused by process variations and external discreteness. The room temperature measured results demonstrate that the achieved saturated output power of 22.3~22.8 dBm with 35.3%~36.5% saturated power-added efficiency (PAE) between 19 GHz and 21 GHz. Especially, the measured IMD3 at 19 GHz, 20 GHz and 21 GHz is below -30 dBc with an output power level of 19 dBm. For a 64-QAM orthogonal frequency division multiplexing signal with 6 dB peak-to-average power ratio and 100 MHz bandwidth，the PA exhibits an adjacent channel power ratio of -31.9 dBc、-33.2 dBc and -31.2 dBc when the error vector magnitude are 4.32%、4.13% and 5.3%.

Key words : adaptive biasing circuit；cold-mode；high linearity；GaAs