| ADC應用中的RCL濾波電路設計 | |
| 所屬分類：電路圖 | |
| 上傳者：hathaway | |
| 文檔大?。?span>308 K | |
| 標簽： 信號調理 | |
| 所需積分：0分積分不夠怎么辦？ | |
| 文檔介紹：Last-stage interfaces to high-speed converters typically have included a simple RC filter as both a noise bandwidth limiting stage and a way to provide a path (through the capacitor) to absorb the sampling glitch coming out of the converter. This simple interface is proving increasingly inadequate as converter SNRs and input analog bandwidths continue to increase. A simple 2ndorder RLC filter can provide both lower noise power bandwidth and more aggressive attenuation of the 3rd-order harmonic distortion at the high end of the analog input range. | |
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