中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.240804 中文引用格式： 李祉怡，孫航，丁學偉，等. Virtuoso iQuantus Insight及Quantus Insight流程在FINFET先進工藝項目中加速后仿迭代的應用[J]. 電子技術應用，2024，50(8)：26-31. 英文引用格式： Li Zhiyi，Sun Hang，Ding Xuewei，et al. Application of Virtuoso iQuantus Insight and Quantus Insight Flow on FINFET advance processes to accelerate post-simulation iteration[J]. Application of Electronic Technique，2024，50(8)：26-31.
Application of Virtuoso iQuantus Insight and Quantus Insight Flow on FINFET advance processes to accelerate post-simulation iteration
Li Zhiyi1，2，Sun Hang1，2，Ding Xuewei1，2，Zhang Huili3，Zeng Yi3
1.Sanechips Technology Co.， Ltd.； 2.State Key Laboratory of Mobile Network and Mobile Multimedia Technology； 3.Cadence Design Systems， Inc.
Abstract： With the evolution of process, the continuous scaling of size introduced more parasitic paths and larger parasitic resistors, causing great differences between the results of post-simulaion and pre-simulation. How to quickly narrow the gap between post-simulation results and pre-simulation results becomes an improtant topic. In traditional design, parasite can only be analyzed through tools like Quantus Extracted View, and the results cannot be displayed in more detail. How to better analyze the parasitic netlist has become a great challange. In addition, after problems found in post-simulation, the design can only be optimized by an iteration process of modifying the circuit design-modifying the layout design-redo the post-simulation. This iteration process is a long period, how to reduce the iteration time cost becomes a key issue for design companies. Virtuoso iQuantus Insight (ViQI)/Quantus Insight (QI) can do accurate parasitic analysis and visuallization based on the parasitic netlist file. Engineers can use this to accurately analyze parasitic parameters, and assume the parasitic values to optimize the design without layout modification. This article describes how to fast iterate the circuit design using ViQI/QI, and so greatly improve work efficiency.
